The great progress has been made in designing and manufacturing computer equipment. The higher speed and better performance of various kinds of processors increase our dependence on computers. Moreover, computer-related skills are essential to students or workers. A monitor is the direct communication medium between a user and a computer. All the information that the user needs from the computer are displayed on the monitor. Hence, not only the speed and the performance of the computer, but also the quality of the monitor should be paid attention to.
In the past, increasing the screen size of the cathode ray tube (CRT) monitor indicates that large volume of the monitor is inevitable. It troubles the user for placing the monitor. Moreover, the radiation of the conventional monitor is harmful to human body. A liquid crystal display (LCD) is developed to solve these problems.
Please refer to FIG. 1(a) showing the structure of a prior art liquid crystal display. The liquid crystal display mainly includes a thin film transistor (TFT) array 100 and a driving circuit. The driving circuit includes a data shift register 105, a scan shift register 110, data switches C1˜Cn, N-bit digital-to-analog converters (DACs) D1˜Dn.
The thin film transistor array 100, consisting of a plurality of display cells E11˜Emn arranged in columns and rows, is the display region of the liquid crystal display. FIG. 1(b) shows one of the display cells. Each display cell includes a capacitor structure 1001 and a thin film transistor 1002. The capacitor structure 1001 is used for storing analog video signals. The thin film transistor array 100 includes plural rows of scan lines and plural columns of data lines. A scan line controls the ON/OFF state of all the thin film transistors 1002 of the display cells in the designated row. Then the data lines transmit analog video signals to the capacitor structures 1001 of the display cells whose thin film transistors 1002 are in an ON state.
The scan shift register 110 consists of a plurality of register units A1˜Am interconnected in series. Each register unit A1˜Am is associated with one of the scan lines. The scan shift register 110 sequentially enables the scan lines to control the ON state of the thin film transistors 1002 row by row.
The data shift register 105 also consists of a plurality of register units B1˜Bn interconnected in series. Each register unit B1˜Bn is associated with one of the data switches C1˜Cn. The data shift register 105 can sequentially switch on data switches C1˜Cn. Each data switch C1˜Cn includes N thin film transistors (only one thin film transistor is shown in FIG. 1(a) for simplicity). Switching on a data switch means digital video signals in the N-bit data line (Din) pass through this data switch simultaneously.
The N-bit digital-to-analog converters D1˜Dn are correspondingly coupled to the data switches C1˜Cn. Each N-bit digital-to-analog converter D1˜Dn receives the digital video signals from the N-bit data line (Din) and converts them into analog video signals when the corresponding data switch C1˜Cn is switched on. Then, the analog video signals are inputted to the corresponding data line of the thin film transistor array 100.
Please refer back to FIG. 1(a). At first, the data switch C1, controlled by the register unit B1 of the data shift register 105, is switched on when a first group of digital video signals are inputted from N-bit data line (Din). Hence, the first group of digital video signals can pass through the data switch C1, and then are converted into the first group of analog video signals by the N-bit digital-to-analog converter D1. Afterwards, the first group of analog video signals get into the data line connecting the display cells E11˜Em1. At the same time, the register unit A1 of the scan shift register 110 enables the scan line connecting the display cells E11˜E1n to switch on the thin film transistors in the display cells E11˜E1n. Hence, the first group analog video signals are stored in the display cell E11.
Next, the data switch C2 is switched on by the register unit B2 of the data shift register 105 when a second group of digital video signals are inputted from N-bit data line (Din). Hence, the second group of digital video signals can pass through the data switch C2, and then are converted into the second group of analog video signals by the N-bit digital-to-analog converter D2. That it, the second group of analog video signals will get into the data line connecting the display cells E12˜Em2. Meanwhile, it is still the scan line connecting the display cells E11˜E1n being driven. Hence, the second group analog video signals are stored in the display cell E12 corresponding to the first row scan line and the second column data line.
The data shift register 105 then sequentially switches on all the following data switches C3˜Cn, and the display cells E13˜E1n in the first row store corresponding groups of analog video signals. After all the display cells E11˜E1n in the first row have stored respective analog video signals, the register unit A2 of the scan shift register 110 is enabled to drive the scan line connecting the display cells E21˜E2n. The analog video signals are stored into the display cells E21˜E2n of the thin film transistor array 100 by means as described above. After the scan shift register 110 enables all the scan lines in turn, all the display cells E11˜Emn of the thin film transistor array 100 have stored analog video signals. Hence, the liquid crystal display shows a full image page on screen.
The analog video signals in every display cell E11˜Emn of the thin film transistor array 100 are refreshed frequently, and that is, the liquid crystal display refreshes images very quickly. What the user see on screen are dynamic images. Certainly, a static image is shown when the analog video signals are refreshed with the same data. Flickers may occur on the liquid crystal display if the refresh rate is too slow.
Please refer to FIG. 1(c) which is a circuit diagram of the data shift register 105/scan shift register 110. The prior art shift register 105 or 110 includes a plurality of flip-flops 120 serving as the register units of FIG. 1(a). The flip-flops 120 are operated in response to a clock signal (CLK) and a start pulse signal (ST) generated by the driving circuit of the liquid crystal display. The flip-flops 120 are controlled by the clock signal (CLK), and then sequentially converts the start pulse signal into enable signals to enable corresponding data switches C1˜Cn or the scan lines. In other words, the driving circuit must generate two clock signals (CLK): one for data shift register 105 and the other one for scan shift register 110. The clock signals (CLK) must be connected to each flip-flop of the shift registers 105 and 110, and thus a great number of pins are required. It is apparent that this requirement complicates the designing and manufacturing of the shift registers 105 and 110. The efforts have been made to develop a better design to solve such problems.